1. Field of the Invention
The present invention relates to detecting errors in compressed data.
2. Discussion of the Background Art
Integrated Circuits (IC) need to be tested to assure proper operation. During test, the IC, as a device under test (DUT), is exposed to stimulus data signals of an Automatic Test Equipment (ATE). The IC transmits corresponding response data back to the ATE. The ATE measures, processes and usually compares this response data with expected responses. The ATE usually performs these tasks according to a device-specific test program.
ATE's with decentralized resources based on a per-pin architecture are known, wherein during test, each pin of a multiple of pins of the DUT is connected to one ATE pin electronic. The per-pin architecture generally enables high performance and scalability. Examples for ATE with per-pin architecture are the Agilent 83000 and 93000 families of Semiconductor Test Systems of Agilent Technologies. Details of those families are also disclosed e.g. in EP-A-859318, EP-A-864977, EP-A-886214, EP-A-882991, U.S. Pat. No. 5,499,248 and U.S. Pat. No. 5,453,995.
With an increasing complexity of Integrated Circuits, the volume of response data becomes larger. In order to reduce test time in the ATE, data compression is used on DUT side combining a plurality of DUT data sequences into a compressed data sequence that is transmitted to the ATE instead of the plurality of data sequences. This allows for reducing the data rate significantly; however, the compressed data sequence does not allow for deriving detailed error or failure information.